FYI: ETH can give a talk on hardware support to prevent timing channels.

Begin forwarded message:

From: "June Andronick (Gmail)" <june.andronick@gmail.com> Subject: Re: Submission to seL4 Summit - Timing Channels Date: 1 June 2022 at 9:24:50 am AEST To: Nils Wistoff <nwistoff@iis.ee.ethz.ch> Cc: summit@sel4.systems, Gernot Heiser <gernot@unsw.edu.au>, Luca Benini <lbenini@iis.ee.ethz.ch>

Hi Nils,

Thanks for your submission! We’ll come back to you once we’ve worked out the program.

Cheers June

...

On 30 May 2022, at 9:01 pm, Nils Wistoff <nwistoff@iis.ee.ethz.ch> wrote:

Dear program committee,

Hereby I would like to apply for a presentation at the seL4 summit 2022.

Title: Hardware Support for Preventing Microarchitectural Timing Channels

Abstract: Microarchitectural timing channels enable information transfer between security domains that are supposed to be isolated, bypassing the operating system's security boundaries. They result from shared microarchitectural state that depends on execution in one security domain and impacts timing in another. Since modern ISAs do not specify timing behaviour, they are insufficient to address these channels.

In this talk, we present fence.t, a novel RISC-V instruction that clears the processor's microarchitectural state and thus any timing dependence on execution history. We show how this instruction was implemented in an open-source RISC-V core and integrated into an experimental version of seL4 with time protection. Furthermore, we will address the challenges of fence.t and its future roadmap.

I am looking forward to your response!

With best regards, Nils Wistoff

-- Nils Wistoff PhD Student Integrated Systems Laboratory (IIS) - ETH Zurich ETZ J85 Gloriastrasse 35 CH-8092 Zurich +41 44 632 06 75 nwistoff@iis.ee.ethz.ch