[seL4] Re: memory zero'ing

On 3/10/23 20:00, Sam Leffler via Devel wrote:

RISC-V (32-bit), no L2 cache. All of user-space shares 1 ASID.

Are you doing any necessary D-cache to I-cache flushing? -- Sincerely, Demi Marie Obenour (she/her/hers)