Hi Wladi, If the problem is with your driver, the problem could be in your management of the INTCTLSTAT register (Chapter 5.10). 1) ARM devices tend to only support 32bit read/write 2) Check that the interrupt enable flag is set before returning from your timer set up code. 3) The status bits must be written as 1 to clear. If interrupts are edge triggered, failing to clear this bit (by writing a 1 to it) will stop interrupts from coming in. 4) Check that your code that clears the interrupt status bit does not clear the enable bit. - Alex Kroh On Tue, 2017-02-21 at 23:17 +0000, Anna.Lyons@data61.csiro.au wrote:
Hey,
First I'd check if the kernel is getting the interrupts in the kernel from this timer - you can put a printf in handleInterrupt in the kernel to see if this is the case and see if the correct interrupt number comes in.
If so, then check if those irqs are being sent to the signal handler and not reserved (again by printing / asserting in handle interrupt).
If not, this points to a problem with your driver.
Hope this pushes you in the right direction, Anna.
-----Original Message----- From: Devel [mailto:devel-bounces@sel4.systems] On Behalf Of Wladislav Wiebe Sent: Wednesday, 22 February 2017 10:05 AM To: devel@sel4.systems Subject: [seL4] ARM timer driver and interrupts
Hello,
I wrote a new timer driver for this timer device: http://www.ti.com/lit/ug/sprugv5a/sprugv5a.pdf
I am already able to run the seL4 testsuite successfully, except the interrupt/timer tests. It waits forever @ wait_for_timer_interrupt(env);
I've uploaded the driver temporary to: https://github.com/wwladikw/devel/blob/master/timer.c
Any idea what could be wrong? I am able to run the timer periodically or as oneshot. The gic_390 interrupt driver in the kernel should also be compatible with the gic_400, for my understanding, right? The SoC I am using contains a Coretex A15.
Thanks a lot in advance! Wladislav Wiebe
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