Just an observation: the CHERI seems to be covered by multiple patents, including an European one. https://patents.google.com/patent/EP3819774B1/en https://copilot.microsoft.com/chats/ta8nCxScGESH7MdGZsubx ----------------------citation------start----------------------------- The CHERI (Capability Hardware Enhanced RISC Instructions) architecture has been adapted to RISC-V, but identifying all patents that specifically cover the RISC-V-related CHERI instruction set is a bit tricky. CHERI itself is a research-driven architecture developed by SRI International and the University of Cambridge, and much of its work has been published openly for academic and security purposes2. However, there are some patents and applications that touch on related technologies: x) U.S. Patent Application #20210365266: Describes a RISC-V implemented processor with hardware acceleration supporting user-defined instruction sets. While not explicitly labeled as CHERI, it may overlap in concept with CHERI-style extensions. x) The CHERI-RISC-V architecture is being refined for standardization, and while the core CHERI work is largely open-source, individual implementations or enhancements by third parties (e.g., hardware vendors) may be patented separately. ----------------------citation------end------------------------------- If the only point of using the RISC-V over ARM was that hardware vendors can produce those chips without needing to pay license fees or be otherwise restricted due to patents, then I really do not understand, why do people bother with the CHERI. A workaround might be to use formal verification of software combined with a patent-free instruction set. Thank You for reading my comment.