Hello Martin, On Thu, 31 Jul 2025 at 10:57, Martin Vahi via Devel <devel@sel4.systems> wrote:
Just an observation: the CHERI seems to be covered by multiple patents, including an European one.
https://patents.google.com/patent/EP3819774B1/en
https://copilot.microsoft.com/chats/ta8nCxScGESH7MdGZsubx ----------------------citation------start----------------------------- The CHERI (Capability Hardware Enhanced RISC Instructions) architecture has been adapted to RISC-V, but identifying all patents that specifically cover the RISC-V-related CHERI instruction set is a bit tricky. CHERI itself is a research-driven architecture developed by SRI International and the University of Cambridge, and much of its work has been published openly for academic and security purposes2.
However, there are some patents and applications that touch on related technologies:
x) U.S. Patent Application #20210365266: Describes a RISC-V implemented processor with hardware acceleration supporting user-defined instruction sets. While not explicitly labeled as CHERI, it may overlap in concept with CHERI-style extensions.
x) The CHERI-RISC-V architecture is being refined for standardization, and while the core CHERI work is largely open-source, individual implementations or enhancements by third parties (e.g., hardware vendors) may be patented separately.
----------------------citation------end-------------------------------
If the only point of using the RISC-V over ARM was that hardware vendors can produce those chips without needing to pay license fees or be otherwise restricted due to patents, then I really do not understand, why do people bother with the CHERI. A workaround might be to use formal verification of software combined with a patent-free instruction set.
This is completely wrong. CHERI as an open ISA extension is similar to RISC-V and is entirely open-source and patent-free (including a fully open specification that is even machine executable and has formally proven properties); you don't need any licence or permission to use or implement it in your processor and there have been many open-source implementations of CHERI. See [1] that has a list of open publications, resources, implementations, etc about CHERI since its inception over the past decade. A hardware vendor can implement RISC-V as an ASIC processor without having a licence or paying and still choose to patent it if they add their own extra accelerators or IP, and that's the same for CHERI. This is exactly what your second search result is saying with regard to CHERI-RISC-V; nothing in your search results suggests that CHERI is patent-protected at all. In this technical report [2], there is an explicit declaration by Cambridge and Arm (Morello) that they have not filed any patents covering the material in the report. [1] https://www.cl.cam.ac.uk/research/security/ctsrd/cheri/ [2] https://www.cl.cam.ac.uk/techreports/UCAM-CL-TR-953.pdf Regards, Hesham
Thank You for reading my comment.
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