There is something else I want to try to do. I got the inspiration
from here: https://community.arm.com/processors/f/discussions/4065/trap-to-hypervisor-i...
It looks like from the ARM Reference manual that if I set the two
least-significant bits of an entry in the first or second level
translation table to be b00, then there will be a page fault any time
that page is accessed. How would I do this in seL4 from the VMM? Is
that currently possible to do?
Thanks!
On Thu, Jun 8, 2017 at 12:26 PM, Mike Clark
Is there any documentation on how the VMM works? If I wanted to start hacking on the VMM and extend its capability, where should I start looking to learn how it works, etc?
That might be a pretty broad topic, because there are lots of ways the VMM can be extended, I'm sure. Broad is fine, until I get things more figured out.