Use sel4 and mmc for storage but sdhc driver wait for SDHC_PRES_STATE_CIHB | SDHC_PRES_STATE_CDIHB
hi there ... i'm working on mmc in sel4 for storage memory. i port your code for i.mx7 (modify registers and all need for that). so when i init mmc with calling mmc_init, sdhc driver wait at sdhc.c@249 and in this line: while (readl(host->base + PRES_STATE) & (SDHC_PRES_STATE_CIHB | SDHC_PRES_STATE_CDIHB)); indeed sdhc driver send function (sdhc_next_cmd(..)) send first command in mmc_reset (): which is : struct mmc_cmd cmd = {.data = NULL}; cmd.index = MMC_GO_IDLE_STATE; cmd.arg = 0; cmd.rsp_type = MMC_RSP_TYPE_NONE; printf("2-1\n"); host_send_command(card, &cmd, NULL, NULL); and status= 65 returned whicm means this command sent completely. so when program continue to send another command (still in mmc_reset) which is : /* TODO: review this command. */ struct mmc_cmd cmd2 = {.data = NULL}; ps_mdelay(10); cmd2.index = MMC_SEND_EXT_CSD; cmd2.arg = 0x1AA; cmd2.rsp_type = MMC_RSP_TYPE_R1; printf("2-2\n"); host_send_command(card, &cmd2, NULL, NULL); status which returned with sdhc send command in sdhc driver is 0. but this worked too. and when program execution continue to call mmc_voltage_validation(..) sdhc driver wait in while (readl(host->base + PRES_STATE) & (SDHC_PRES_STATE_CIHB | SDHC_PRES_STATE_CDIHB)); ... I don't have any idea why this happened .. can you help me? I didn't modify any code in sdhc.c or mmc.c ... my app for using mmc is here: #include <autoconf.h> #include <camkes.h> #include <camkes/io.h> #include <camkes/sync.h> #include <stdio.h> #include <utils/util.h> #include "string.h" //sdio test #include <sdhc/mmc.h> #include <sdhc/plat/sdio.h> #include <sdhc/sdio.h> #define max(x, y) (((x) >= (y)) ? (x) : (y)) //build config // #define TEST_FILESYSTEM 0 #ifdef CONFIG_64BIT #define BITS_PER_LONG 64 #else #define BITS_PER_LONG 32 #endif /* CONFIG_64BIT */ #define IMX7_GPIO1_BASE_ADDR ((uint32_t)NULL) #define IMX7_GPIO4_BASE_ADDR ((uint32_t)NULL) #define IMX7_SPI_BASE_ADDR ((uint32_t)NULL) #define IMX7_CTL_MUX_BASE_ADDR ((uint32_t)NULL) /** * we have two keyboard driver () */ bool STDKBD = true; #define IMX7_CTL_MUX_GPIO1_09 (0x18) seL4_CPtr timer_notification(void); seL4_CPtr notification; static void delay(uint64_t ms) { seL4_Word badge; /* test a relative timeout */ uint64_t t1 = timer_time(); // printf("Cur time: %"PRIu64"\n", t1); timer_oneshot_relative(0, ms * NS_IN_MS); seL4_Wait(notification, &badge); // printf("Badge: %x\n", badge); t1 = timer_time(); // printf("Cur time: %"PRIu64"\n", t1); } /* * Required for the camkes_sys_clock_gettime() in sys_clock.c of libsel4camkes. */ int clk_get_time(void) { uint64_t time_in_ms = timer_time() / NS_IN_MS; return (time_in_ms & 0xFFFFFFFF); } static int count = 0; ps_io_ops_t io_ops = {0}; struct netif* net_if; mmc_card_t mmc_card = 0; sdio_host_dev_t sdio_host_dev; int mmc_found = 0; void mmc_irq_handle(ps_irq_t* irq) { printf("mmc irq handle .... \n"); if(!mmc_found){ // printf("mmc not found yet :)\n"); // mmc_init handle this self // sdio_host_dev.handle_irq(&sdio_host_dev,irq->irq.number); mmc_irq_acknowledge(irq); return ; } // sdio_host.handle_irq(&sdio_host, irq); mmc_handle_irq(mmc_card,irq->irq.number); mmc_irq_acknowledge(irq); } int run(void) { notification = timer_notification(); int err = camkes_io_ops(&io_ops); if (err != 0) { ZF_LOGF("Can not init ops : %d\n", err); }; printf("initialize sdhc1 ...\n"); err = sdio_init(SDHC1, &io_ops, &sdio_host_dev); // while card not present check while(sdio_host_dev.reset(&sdio_host_dev) == -1){ delay(1000); } printf("before mmc_init\n"); mmc_init(&sdio_host_dev, &io_ops, &mmc_card); mmc_found = 1; printf("after mmc_init\n"); if (!err) { printf("SDHC1 inited successfully.\n"); // sdhc_ls(); } else { printf("SDHC1 initizatino failed!: %d", err); } // sdio_host_dev.reset(&sdio_host_dev); // mmc_init(&sdio_host_dev, &io_ops, mmc_card); // sdio_host_dev.handle_irq =mmc_handle_irq_func; while (true) { printf(".\n"); delay(1000); } return 0; } best regards.. shafie -- This email was Anti Virus checked by Security Gateway.
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MOHAMAD REZA SHAFIEI