loading and booting seL4 on a tegra Tx2
Hi, I am trying to bring up sel4 on tegra Tx2 platform using tegra Tx1 as reference. I tweaked the important changes of UART,Timer configuration and IRQ number and also GIC controller, GIC distributor configuration w.r.t Tx2 after loading and booting the Tx2 board sel4 enter into init kernel to initialize the kerenl memory map for GIC and UART devices then control transfer to user space. I underdtand from ref manual both Tx1 and Tx2 using the same clock and baud rate for UART configuration. ## Starting application at 0x82000000 ... ELF-loader started on CPU: ARM Ltd. Cortex-A57 r1p3 paddr=[82000000..827abfff] kernel_phys_start: 0xffffffff80000000 kernel_phys_end:0xffffffff8022fcdf load_elf : image_size 0x230000 ELF-loading image 'kernel' paddr=[80000000..8022ffff] vaddr=[ffffff8000000000..ffffff800022ffff] virt_entry=ffffff8000000000 load_elf : image_size 0x5e9000 ELF-loading image 'sel4test-driver' paddr=[80230000..80818fff] vaddr=[400000..9e8fff] virt_entry=41b160 Enabling MMU and paging Jumping to kernel-image entry point... Also try to add debug print in the init kernel thread to understand the virtual memory set-up but its crashed with synchronous exception. It indicates that the UART driver till not available to log the messages this was seen in Tx1 and Tx2. Not able to check/debug further on this issue. Also experimented with various arbitrary address for UARTA_PPTR and GIC_PPTR because Tx1 UARTA has 64byte size in case of Tx2 its 1MB.but still nothing has improved the state remain same. I completely walk through the sel4 boot and arm MMU code.I do not see any board specific changes in this code apart from UART,GIC configuration and IRQ number. The assembly code of MMU mainly setting up TCR ,TTBR , TLB invalidation and pagetable setup for arma-57. Please let me know your thought on this issue and how do debug this kind of issue. Regards, Munees
Hi Munees, I am afraid I can't be much help, but I can offer some tips for debug printing. The elfloader boots the kernel with unity mappings. If you would like to use debug printing before the kernel maps the serial port, try changing UARTA_PPTR to UARTA_PADDR in the UART driver: https://github.com/seL4/seL4/blob/master/src/plat/tx1/machine/io.c#L23 - Alex On Sat, 2017-11-11 at 11:26 +0530, Muneeswaran Rajendran wrote:
Hi,
I am trying to bring up sel4 on tegra Tx2 platform using tegra Tx1 as reference.
I tweaked the important changes of UART,Timer configuration and IRQ number and also GIC controller, GIC distributor configuration w.r.t Tx2
after loading and booting the Tx2 board sel4 enter into init kernel to initialize the kerenl memory map for GIC and UART devices then control transfer to user space. I underdtand from ref manual both Tx1 and Tx2 using the same clock and baud rate for UART configuration.
## Starting application at 0x82000000 ...
ELF-loader started on CPU: ARM Ltd. Cortex-A57 r1p3 paddr=[82000000..827abfff] kernel_phys_start: 0xffffffff80000000 kernel_phys_end:0xffffffff8022fcdf load_elf : image_size 0x230000 ELF-loading image 'kernel' paddr=[80000000..8022ffff] vaddr=[ffffff8000000000..ffffff800022ffff] virt_entry=ffffff8000000000 load_elf : image_size 0x5e9000 ELF-loading image 'sel4test-driver' paddr=[80230000..80818fff] vaddr=[400000..9e8fff] virt_entry=41b160 Enabling MMU and paging Jumping to kernel-image entry point...
Also try to add debug print in the init kernel thread to understand the virtual memory set-up but its crashed with synchronous exception.
It indicates that the UART driver till not available to log the messages this was seen in Tx1 and Tx2. Not able to check/debug further on this issue.
Also experimented with various arbitrary address for UARTA_PPTR and GIC_PPTR because Tx1 UARTA has 64byte size in case of Tx2 its 1MB.but still nothing has improved the state remain same.
I completely walk through the sel4 boot and arm MMU code.I do not see any board specific changes in this code apart from UART,GIC configuration and IRQ number. The assembly code of MMU mainly setting up TCR ,TTBR , TLB invalidation and pagetable setup for arma-57.
Please let me know your thought on this issue and how do debug this kind of issue.
Regards, Munees
_______________________________________________ Devel mailing list Devel@sel4.systems https://sel4.systems/lists/listinfo/devel
Thanks alex.
I try to boot sel4 kernel on Tx2 with minimal config.
I seen that after kernel memory map and during CPU initialisation try to
setup the global page directory and invalidating the local TLB entry
(invalidateLocalTLB()) then cpu hangs and controls not come out.
I understand from that instruction (tlbi vmalle1) from ARM manual It's try
to 'invalidate stage 1 entries associated to the current VMID'
Also referred the arm mmu code in seL4 and it's setting up the TCR register
addressing space(48bit),ASID as 16bit and page table setup 4k granular size.
Any suggestion or pointers how to address this type of hang issues in seL4
kernel?
Regards,
Munees
On Sun, Nov 12, 2017 at 3:23 AM,
Hi Munees,
I am afraid I can't be much help, but I can offer some tips for debug printing.
The elfloader boots the kernel with unity mappings. If you would like to use debug printing before the kernel maps the serial port, try changing UARTA_PPTR to UARTA_PADDR in the UART driver: https://github.com/seL4/seL4/blob/master/src/plat/tx1/machine/io.c#L23
- Alex
On Sat, 2017-11-11 at 11:26 +0530, Muneeswaran Rajendran wrote:
Hi,
I am trying to bring up sel4 on tegra Tx2 platform using tegra Tx1 as reference.
I tweaked the important changes of UART,Timer configuration and IRQ number and also GIC controller, GIC distributor configuration w.r.t Tx2
after loading and booting the Tx2 board sel4 enter into init kernel to initialize the kerenl memory map for GIC and UART devices then control transfer to user space. I underdtand from ref manual both Tx1 and Tx2 using the same clock and baud rate for UART configuration.
## Starting application at 0x82000000 ...
ELF-loader started on CPU: ARM Ltd. Cortex-A57 r1p3 paddr=[82000000..827abfff] kernel_phys_start: 0xffffffff80000000 kernel_phys_end:0xffffffff8022fcdf load_elf : image_size 0x230000 ELF-loading image 'kernel' paddr=[80000000..8022ffff] vaddr=[ffffff8000000000..ffffff800022ffff] virt_entry=ffffff8000000000 load_elf : image_size 0x5e9000 ELF-loading image 'sel4test-driver' paddr=[80230000..80818fff] vaddr=[400000..9e8fff] virt_entry=41b160 Enabling MMU and paging Jumping to kernel-image entry point...
Also try to add debug print in the init kernel thread to understand the virtual memory set-up but its crashed with synchronous exception.
It indicates that the UART driver till not available to log the messages this was seen in Tx1 and Tx2. Not able to check/debug further on this issue.
Also experimented with various arbitrary address for UARTA_PPTR and GIC_PPTR because Tx1 UARTA has 64byte size in case of Tx2 its 1MB.but still nothing has improved the state remain same.
I completely walk through the sel4 boot and arm MMU code.I do not see any board specific changes in this code apart from UART,GIC configuration and IRQ number. The assembly code of MMU mainly setting up TCR ,TTBR , TLB invalidation and pagetable setup for arma-57.
Please let me know your thought on this issue and how do debug this kind of issue.
Regards, Munees
_______________________________________________ Devel mailing list Devel@sel4.systems https://sel4.systems/lists/listinfo/devel
participants (2)
-
Alexander.Kroh＠data61.csiro.au -
Muneeswaran Rajendran