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Kelly Dean

8 Mar 2018 8 Mar '18

5 a.m.

The RISC-V privileged ISA is not yet finalized. Have the seL4 developers reviewed the draft [1], in case they might have any recommendations for improvement? For example, just last year a blunder (H-mode) was removed from the draft per a proposal [2] on the mailing list. Finalization is planned for this year. Speak now or forever hold your peace. The first public draft of the memory consistency model [3] was also released just last December. And platform standardization, especially the IOMMU, is in progress. [1] https://content.riscv.org/wp-content/uploads/2017/05/riscv-privileged-v1.10.... [2] https://groups.google.com/a/groups.riscv.org/forum/#!msg/isa-dev/SfEDPLU0NU4... [3] https://groups.google.com/a/groups.riscv.org/forum/#!topic/isa-dev/hKywNHBkA...

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Gernot.Heiser＠data61.csiro.au

8 Mar 8 Mar

4:18 p.m.

Yes, RISC-V specs are high on my priorities. I’ll actually participate in some of the working groups. Gernot

On 8 Mar 2018, at 05:00, Kelly Dean wrote:

The RISC-V privileged ISA is not yet finalized. Have the seL4 developers reviewed the draft [1], in case they might have any recommendations for improvement?

For example, just last year a blunder (H-mode) was removed from the draft per a proposal [2] on the mailing list.

Finalization is planned for this year. Speak now or forever hold your peace.

The first public draft of the memory consistency model [3] was also released just last December.

And platform standardization, especially the IOMMU, is in progress.

[1] https://content.riscv.org/wp-content/uploads/2017/05/riscv-privileged-v1.10.... [2] https://groups.google.com/a/groups.riscv.org/forum/#!msg/isa-dev/SfEDPLU0NU4... [3] https://groups.google.com/a/groups.riscv.org/forum/#!topic/isa-dev/hKywNHBkA...

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Corey Richardson

5:47 p.m.

I'm so happy to hear this! On Thu, Mar 8, 2018, at 00:18, Gernot.Heiser@data61.csiro.au wrote:

Yes, RISC-V specs are high on my priorities. I’ll actually participate in some of the working groups.

Gernot

...
On 8 Mar 2018, at 05:00, Kelly Dean wrote:

The RISC-V privileged ISA is not yet finalized. Have the seL4 developers reviewed the draft [1], in case they might have any recommendations for improvement?

For example, just last year a blunder (H-mode) was removed from the draft per a proposal [2] on the mailing list.

Finalization is planned for this year. Speak now or forever hold your peace.

The first public draft of the memory consistency model [3] was also released just last December.

And platform standardization, especially the IOMMU, is in progress.

[1] https://content.riscv.org/wp-content/uploads/2017/05/riscv-privileged-v1.10.... [2] https://groups.google.com/a/groups.riscv.org/forum/#!msg/isa-dev/SfEDPLU0NU4... [3] https://groups.google.com/a/groups.riscv.org/forum/#!topic/isa-dev/hKywNHBkA...

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Matthew Wilson

9 Mar 9 Mar

2:29 a.m.

I'm also extremely happy to hear this.. Looking forward to reasonable (or at least effable) specs! On Wed, Mar 7, 2018 at 11:47 PM, Corey Richardson wrote:

I'm so happy to hear this!

...
Yes, RISC-V specs are high on my priorities. I’ll actually participate in some of the working groups.

Gernot

...
On 8 Mar 2018, at 05:00, Kelly Dean wrote:

The RISC-V privileged ISA is not yet finalized. Have the seL4 developers reviewed the draft [1], in case they might have any recommendations for improvement?

For example, just last year a blunder (H-mode) was removed from the draft per a proposal [2] on the mailing list.

Finalization is planned for this year. Speak now or forever hold your

On Thu, Mar 8, 2018, at 00:18, Gernot.Heiser@data61.csiro.au wrote: peace.

...
...
The first public draft of the memory consistency model [3] was also

released just last December.

...
And platform standardization, especially the IOMMU, is in progress.

[1] https://content.riscv.org/wp-content/uploads/2017/05/riscv-p

rivileged-v1.10.pdf

...
[2] https://groups.google.com/a/groups.riscv.org/forum/#!msg/isa -dev/SfEDPLU0NU4/WpAE_A4OBQAJ [3] https://groups.google.com/a/groups.riscv.org/forum/#!topic/ isa-dev/hKywNHBkAXM

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Devel mailing list Devel@sel4.systems https://sel4.systems/lists/listinfo/devel

-- cmr http://octayn.net/ +16038524272

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George Hansel

14 Mar 14 Mar

12:14 p.m.

Are there any formal models of the ISA currently, or planned? I'd be interested in working on one if so - currently mulling what it would take to port seL4 to privileged-RISC, with the new availability of silicon that implements some portion of its draft. On Thu, Mar 8, 2018 at 7:29 AM, Matthew Wilson wrote:

I'm also extremely happy to hear this.. Looking forward to reasonable (or at least effable) specs!

On Wed, Mar 7, 2018 at 11:47 PM, Corey Richardson wrote:

...
I'm so happy to hear this!

...
Yes, RISC-V specs are high on my priorities. I’ll actually participate in some of the working groups.

Gernot

...
On 8 Mar 2018, at 05:00, Kelly Dean wrote:

The RISC-V privileged ISA is not yet finalized. Have the seL4 developers reviewed the draft [1], in case they might have any recommendations for improvement?

For example, just last year a blunder (H-mode) was removed from the draft per a proposal [2] on the mailing list.

Finalization is planned for this year. Speak now or forever hold your

On Thu, Mar 8, 2018, at 00:18, Gernot.Heiser@data61.csiro.au wrote: peace.

...
...
The first public draft of the memory consistency model [3] was also

released just last December.

...
And platform standardization, especially the IOMMU, is in progress.

[1] https://content.riscv.org/wp-content/uploads/2017/05/riscv-p

rivileged-v1.10.pdf

...
[2] https://groups.google.com/a/groups.riscv.org/forum/#!msg/isa -dev/SfEDPLU0NU4/WpAE_A4OBQAJ [3] https://groups.google.com/a/groups.riscv.org/forum/#!topic/i sa-dev/hKywNHBkAXM

_______________________________________________ Devel mailing list Devel@sel4.systems https://sel4.systems/lists/listinfo/devel

Devel mailing list Devel@sel4.systems https://sel4.systems/lists/listinfo/devel

-- cmr http://octayn.net/ +16038524272

_______________________________________________ Devel mailing list Devel@sel4.systems https://sel4.systems/lists/listinfo/devel

-- Sent by an Internet

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Gerwin.Klein＠data61.csiro.au

1:59 p.m.

We are looking at using this one: https://github.com/SRI-CSL/l3riscv I haven't reviewed it yet, it might not contain much of privileged mode yet. Cheers, Gerwin On 14 Mar 2018, at 12:14, George Hansel mailto:george.hansel@gmail.com> wrote: Are there any formal models of the ISA currently, or planned? I'd be interested in working on one if so - currently mulling what it would take to port seL4 to privileged-RISC, with the new availability of silicon that implements some portion of its draft. On Thu, Mar 8, 2018 at 7:29 AM, Matthew Wilson mailto:diakopter@gmail.com> wrote: I'm also extremely happy to hear this.. Looking forward to reasonable (or at least effable) specs! On Wed, Mar 7, 2018 at 11:47 PM, Corey Richardson mailto:corey@octayn.net> wrote: I'm so happy to hear this! On Thu, Mar 8, 2018, at 00:18, Gernot.Heiser@data61.csiro.aumailto:Gernot.Heiser@data61.csiro.au wrote:

Yes, RISC-V specs are high on my priorities. I’ll actually participate in some of the working groups.

Gernot

...
On 8 Mar 2018, at 05:00, Kelly Dean mailto:kelly@prtime.org> wrote:

The RISC-V privileged ISA is not yet finalized. Have the seL4 developers reviewed the draft [1], in case they might have any recommendations for improvement?

For example, just last year a blunder (H-mode) was removed from the draft per a proposal [2] on the mailing list.

Finalization is planned for this year. Speak now or forever hold your peace.

The first public draft of the memory consistency model [3] was also released just last December.

And platform standardization, especially the IOMMU, is in progress.

[1] https://content.riscv.org/wp-content/uploads/2017/05/riscv-privileged-v1.10.... [2] https://groups.google.com/a/groups.riscv.org/forum/#!msg/isa-dev/SfEDPLU0NU4... [3] https://groups.google.com/a/groups.riscv.org/forum/#!topic/isa-dev/hKywNHBkA...

_______________________________________________ Devel mailing list Devel@sel4.systemsmailto:Devel@sel4.systems https://sel4.systems/lists/listinfo/devel

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participants (6)

Corey Richardson
George Hansel
Gernot.Heiser＠data61.csiro.au
Gerwin.Klein＠data61.csiro.au
Kelly Dean
Matthew Wilson