Hi all, I'm looking into getting seL4 booting on 32 bit RISC-V. Currently working with seL4test 10.1.1, QEMU 4.0.0, and an upstream copy of riscv-gnu-toolchain (is there a specific release I should try?). I'm able to get seL4 to build after deleting a few CONST labels that the compiler was complaining about, but when I try to run the simulation script, I get the following output:
Are there any tricks for getting this working right now? Thanks, Baltazar ________________________________ Notice: This email and any attachments may contain proprietary (Draper non-public) and/or export-controlled information of Draper. If you are not the intended recipient of this email, please immediately notify the sender by replying to this email and immediately destroy all copies of this email. ________________________________
Hi Baltazar, To get that version of seL4 working, you should use an obsolete version of the RISC-V toolchain. Follow the instructions here, https://docs.sel4.systems/Hardware/RISCV.html If you prefer to use the upstream riscv-gnu-toolchain, you need to checkout the latest sel4test-manifest. In either case, modifying the seL4 source code shouldn't be required. Regards, Siwei On Mon, 2019-07-29 at 21:36 +0000, Ortiz, Baltazar wrote:
Thanks for the response! I tried using the latest sel4test and got the same assertion failure. I once again had to remove the two CONST labels from thread.h to fix the below error.
I'm going to build the 64 bit version of the toolchain and see if that works any better than the 32 bit. Worst case, I'll give the obsolete version of the toolchain another shot, though I had trouble getting it set up in the past. Thanks, Baltazar -----Original Message----- From: Devel <devel-bounces@sel4.systems> On Behalf Of Zhuang, Siwei (Data61, Kensington NSW) Sent: Monday, July 29, 2019 10:28 PM To: devel@sel4.systems Subject: Re: [seL4] SeL4 on 32 bit RISC-V Hi Baltazar, To get that version of seL4 working, you should use an obsolete version of the RISC-V toolchain. Follow the instructions here, https://docs.sel4.systems/Hardware/RISCV.html If you prefer to use the upstream riscv-gnu-toolchain, you need to checkout the latest sel4test-manifest. In either case, modifying the seL4 source code shouldn't be required. Regards, Siwei On Mon, 2019-07-29 at 21:36 +0000, Ortiz, Baltazar wrote:
Devel mailing list Devel@sel4.systems https://sel4.systems/lists/listinfo/devel ________________________________ Notice: This email and any attachments may contain proprietary (Draper non-public) and/or export-controlled information of Draper. If you are not the intended recipient of this email, please immediately notify the sender by replying to this email and immediately destroy all copies of this email. ________________________________
Quick update - I had to build the toolchain with the "--with-arch=rv32gc --with-abi=ilp32" flags. seL4test now runs and passes all but the FPU tests. -----Original Message----- From: Ortiz, Baltazar Sent: Wednesday, July 31, 2019 2:01 PM To: 'Zhuang, Siwei (Data61, Kensington NSW)' <Siwei.Zhuang@data61.csiro.au>; devel@sel4.systems Subject: RE: [seL4] SeL4 on 32 bit RISC-V Thanks for the response! I tried using the latest sel4test and got the same assertion failure. I once again had to remove the two CONST labels from thread.h to fix the below error.
I'm going to build the 64 bit version of the toolchain and see if that works any better than the 32 bit. Worst case, I'll give the obsolete version of the toolchain another shot, though I had trouble getting it set up in the past. Thanks, Baltazar -----Original Message----- From: Devel <devel-bounces@sel4.systems> On Behalf Of Zhuang, Siwei (Data61, Kensington NSW) Sent: Monday, July 29, 2019 10:28 PM To: devel@sel4.systems Subject: Re: [seL4] SeL4 on 32 bit RISC-V Hi Baltazar, To get that version of seL4 working, you should use an obsolete version of the RISC-V toolchain. Follow the instructions here, https://docs.sel4.systems/Hardware/RISCV.html If you prefer to use the upstream riscv-gnu-toolchain, you need to checkout the latest sel4test-manifest. In either case, modifying the seL4 source code shouldn't be required. Regards, Siwei On Mon, 2019-07-29 at 21:36 +0000, Ortiz, Baltazar wrote:
Devel mailing list Devel@sel4.systems https://sel4.systems/lists/listinfo/devel ________________________________ Notice: This email and any attachments may contain proprietary (Draper non-public) and/or export-controlled information of Draper. If you are not the intended recipient of this email, please immediately notify the sender by replying to this email and immediately destroy all copies of this email. ________________________________
On Fri, 2 Aug 2019 at 17:07, Ortiz, Baltazar <bortiz@draper.com> wrote:
Quick update - I had to build the toolchain with the "--with-arch=rv32gc --with-abi=ilp32" flags. seL4test now runs and passes all but the FPU tests.
The seL4 RISC-V port doesn't support FPU yet. You will need "--with-arch=rv32imac --with-abi=ilp32" or --enable-multilib for the FPU tests not to generate FPU instructions.
-- Hesham
Thanks! -----Original Message----- From: Hesham Almatary <heshamelmatary@gmail.com> Sent: Friday, August 9, 2019 5:30 AM To: Ortiz, Baltazar <bortiz@draper.com>; seL4 <devel@sel4.systems> Subject: Re: [seL4] SeL4 on 32 bit RISC-V On Fri, 2 Aug 2019 at 17:07, Ortiz, Baltazar <bortiz@draper.com> wrote:
Quick update - I had to build the toolchain with the "--with-arch=rv32gc --with-abi=ilp32" flags. seL4test now runs and passes all but the FPU tests.
The seL4 RISC-V port doesn't support FPU yet. You will need "--with-arch=rv32imac --with-abi=ilp32" or --enable-multilib for the FPU tests not to generate FPU instructions.
-- Hesham ________________________________ Notice: This email and any attachments may contain proprietary (Draper non-public) and/or export-controlled information of Draper. If you are not the intended recipient of this email, please immediately notify the sender by replying to this email and immediately destroy all copies of this email. ________________________________
participants (3)
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Hesham Almatary -
Ortiz, Baltazar -
Zhuang, Siwei (Data61, Kensington NSW)