-----邮件原件----- 发件人: devel-request@sel4.systems [mailto:devel-request@sel4.systems] 发送时间: 2021年11月18日 5:56 收件人: devel@sel4.systems 主题: Devel Digest, Vol 125, Issue 2
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Today's Topics:
1. Re: some question about seL4 performance (Gerwin Klein) 2. Re: some question about seL4 performance (Gernot Heiser) 3. Re: some question about seL4 performance (Gerwin Klein)
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Message: 1 Date: Wed, 17 Nov 2021 21:24:57 +0000 From: Gerwin Klein kleing@unsw.edu.au Subject: [seL4] Re: some question about seL4 performance To: yadong.li yadong.li@horizon.ai Cc: "devel@sel4.systems" devel@sel4.systems Message-ID: CA210292-C334-42C1-9FB4-48CAFDE8CCC6@unsw.edu.au Content-Type: text/plain; charset="utf-8"
On 18 Nov 2021, at 02:06, yadong.li yadong.li@horizon.ai wrote:
Hi： I learn the sel4 performance form https://sel4.systems/About/Performance/ I focus on the ARMv8 platform, from the website, the parameters are as follows: ISA Mode Core/SoC/Board Clock IRQ Invoke IPC call IPC reply "Armv8a 64 A57/Tx1/Jetson 1.9 GHz 863 (18) 396(15) 397(4)"
I want to know what is the length of IPC for the record provided on the web page , when test IPC call and reply? 0 or 10?
The page reports the 0-length numbers. The idea is that IPC should fit into registers, the 10 case is the one that make it spill into memory deliberately. That number is good to know for development, but should not be the main performance characteristic.
Cheers, Gerwin
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Message: 2 Date: Wed, 17 Nov 2021 21:36:39 +0000 From: Gernot Heiser gernot@unsw.edu.au Subject: [seL4] Re: some question about seL4 performance To: "devel@sel4.systems" devel@sel4.systems Message-ID: 9885F4AB-61C0-46CD-B239-595E38482673@unsw.edu.au Content-Type: text/plain; charset="utf-8"
On 18 Nov 2021, at 08:24, Gerwin Klein kleing@unsw.edu.au wrote:
The page reports the 0-length numbers. The idea is that IPC should fit into registers, the 10 case is the one that make it spill into memory deliberately. That number is good to know for development, but should not be the main performance characteristic.
Note that whether data is transferred solely in registers or using a memory buffer does not make a big difference on contemporary hardware. However, our present implementation reverts to the slow path as soon as the message size overflows the physical message registers, which will make the PIC much slower.
This is something that could be fixed by widening the fastpath conditions without much complications. However, we haven’t yet come across an important use case where this matters, so there isn’t much motivation for investing time in it.
Gernot
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Message: 3 Date: Wed, 17 Nov 2021 21:56:06 +0000 From: Gerwin Klein kleing@unsw.edu.au Subject: [seL4] Re: some question about seL4 performance To: Gernot Heiser gernot@unsw.edu.au Cc: "devel@sel4.systems" devel@sel4.systems Message-ID: FFD95815-9F62-4A90-A3D0-59671152494D@unsw.edu.au Content-Type: text/plain; charset="us-ascii"
On 18 Nov 2021, at 08:36, Gernot Heiser <gernot@unsw.edu.aumailto:gernot@unsw.edu.au> wrote:
On 18 Nov 2021, at 08:24, Gerwin Klein <kleing@unsw.edu.aumailto:kleing@unsw.edu.au> wrote:
The page reports the 0-length numbers. The idea is that IPC should fit into registers, the 10 case is the one that make it spill into memory deliberately. That number is good to know for development, but should not be the main performance characteristic.
Note that whether data is transferred solely in registers or using a memory buffer does not make a big difference on contemporary hardware. However, our present implementation reverts to the slow path as soon as the message size overflows the physical message registers, which will make the PIC much slower.
Yes I should have mentioned that. If you look at the raw numbers for x86, eg. at https://github.com/seL4/sel4bench/actions/runs/1469475721#artifacts, fast path/no fast path is almost equal for length 10. You get a tiny bit better performance for length 10 when the fast path is switched off completely, because it doesn't first have to test whether to take the fast path or not.
Cheers, Gerwin
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