On 19 May 2017, at 04:18, Andrew Gacek andrew.gacek@gmail.com wrote:
Is there any support for seL4 on the Cortex-A5?
I’m fairly confident that no-one here has tested this. FWICT, it should be ISA compatible with the A7/A15, but no virtualisation support. Means it should probably work in supervisor mode, but there’s no hyp mode.
Gernot
Andrew,
As part of a Phase I SBIR and commercial project, we ported an earlier version of seL4 to the Cortex-A5. The A5 is very similar to the A7 and A15 without hyp mode; however, the L1 cache line size is 32 bytes (see include/arch/arm/arch/32/mode/machine/hardware.h and http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0433c/CIHDHAB...). This is all you should need to change.
Brian
On 05/18/2017 01:18 PM, Andrew Gacek wrote:
Is there any support for seL4 on the Cortex-A5?
-Andrew
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Andrew Gacek -
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Gernot.Heiser＠data61.csiro.au