On 30 Nov 2018, at 22:06, 송대영 <scribnote5(a)gmail.com> wrote:
Hi, I read "Improving Interrupt Response Time in a Verifiable Protected
This paper improved IPC performance by using cache pinning and I want to know how to
implement cache pinnng.
But this paper doesn't refer how to manipulate cache lines.
Cache pinning is an architecture- (or sometimes implementation-) specific features. It’s
available on some processors but not on others. It’s got nothing to do with the kernel.
Would you give me some methods how to read cache lines
and write cache lines?
by doing loads and stores