Re: [seL4] seL4 developer review of RISC-V privileged ISA spec?

I'm so happy to hear this! On Thu, Mar 8, 2018, at 00:18, Gernot.Heiser@data61.csiro.au wrote:

Yes, RISC-V specs are high on my priorities. I’ll actually participate in some of the working groups.

Gernot

...

On 8 Mar 2018, at 05:00, Kelly Dean wrote:

The RISC-V privileged ISA is not yet finalized. Have the seL4 developers reviewed the draft [1], in case they might have any recommendations for improvement?

For example, just last year a blunder (H-mode) was removed from the draft per a proposal [2] on the mailing list.

Finalization is planned for this year. Speak now or forever hold your peace.

The first public draft of the memory consistency model [3] was also released just last December.

And platform standardization, especially the IOMMU, is in progress.

[1] https://content.riscv.org/wp-content/uploads/2017/05/riscv-privileged-v1.10.... [2] https://groups.google.com/a/groups.riscv.org/forum/#!msg/isa-dev/SfEDPLU0NU4... [3] https://groups.google.com/a/groups.riscv.org/forum/#!topic/isa-dev/hKywNHBkA...

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