19 May
2017
19 May
'17
8:48 a.m.
Andrew, As part of a Phase I SBIR and commercial project, we ported an earlier version of seL4 to the Cortex-A5. The A5 is very similar to the A7 and A15 without hyp mode; however, the L1 cache line size is 32 bytes (see include/arch/arm/arch/32/mode/machine/hardware.h and http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0433c/CIHDHAB...). This is all you should need to change. Brian On 05/18/2017 01:18 PM, Andrew Gacek wrote:
Is there any support for seL4 on the Cortex-A5?
-Andrew
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