Hi Arun and Anna,
seL4 32-bit support should just work as good as 64-bit. The question
is which tools and platform you are using (specifically how riscv-pk
prints characters):
If you're using the riscv-tools/master branch to build the tools, this
won't work for a few reasons:
* The port relies on the HTIF interface for printing out. There's an
issue with riscv-pk when dealing with 32-bit HTIF commands here [1]
* There's no official support for 32-bit Linux and riscv-pk with HTIF AFAIK
* When I last built spike from riscv-tools/master (and not
riscv-tools/priv-1.10) cpu0 was masked/disabled from spike/dtb and
loops indefinitely
* riscv-pk seems to change the way it prints things (diff priv-1.10 > master)
https://github.com/riscv/riscv-pk/pull/94
https://github.com/riscv/riscv-pk/issues/92
If you still want to run the 32-bit of the seL4 kernel on simulators,
I'd advise you to:
1- Follow this script [2] when installing the tools. What this script
does differently is that it builds the riscv-tools/priv-1.10 (given
that the seL4/RISC-V port is priv-1.10 and I have tested 32-bit seL4
with these revisions of the tools)
2- Apply this patch [3] to riscv-pk before building (to fix/hack
around the 32-bit HTIF issue above)
3- Build 32-bit toolchain (./build-rv32ima.sh)
P.S. If you have a real HW platform that just uses UART instead of
HTIF, that won't be a problem.
[1] https://github.com/riscv/riscv-pk/pull/84
[2] https://github.com/heshamelmatary/riscv-sel4/blob/master/test_sel4riscv.sh
[3] https://github.com/riscv/riscv-pk/pull/84.patch
On Thu, Apr 19, 2018 at 4:27 AM,
Hi Arun,
32-bit RISC-V is not scheduled on our roadmap currently, unless it's required for another project.
Code for 32-bit RISC-V is there for the kernel and user-level, and currently compiles. But the
kernel doesn't successfully boot and needs investigation. A community contribution is welcome :).
Thanks
Anna.
________________________________ From: Devel
on behalf of Arun Thomas Sent: Thursday, 19 April 2018 1:17 PM To: Mcleod, Kent (Data61, Kensington NSW) Cc: devel@sel4.systems Subject: Re: [seL4] Announcing seL4 9.0.1: with RISC-V support Congrats on the new release! I'm very excited to see upstream support for RISC-V.
Out of curiosity, is there a timeline for 32-bit RISC-V support?
Thanks, Arun
On Wed, Apr 18, 2018 at 12:11 AM
wrote: We are pleased to announce initial RISC-V support for the UC Berkeley Spike simulator platform.
Instructions are available for building and running the seL4 test suite on RISC-V: https://docs.sel4.systems/Hardware/RISCV
See an online copy of the release notes at: https://docs.sel4.systems/sel4_release/seL4_9.0.1 https://docs.sel4.systems/camkes_release/CAmkES_3.4.0
# seL4 Version 9.0.1 Release Announcing the release of `seL4 9.0.1` with the following changes:
9.0.1 2018-04-18: BINARY COMPATIBLE
## Changes * On 64-bit architectures, the `label` field of `seL4_MessageInfo` is now 52 bits wide. User-level programs which use any of the following functions may break, if the program relies on these functions to mask the `label` field to the previous width of 20 bits. - `seL4_MessageInfo_new` - `seL4_MessageInfo_get_label` - `seL4_MessageInfo_set_label` * Initial prototype RISC-V architecture port. This port currently only supports running in 64-bit mode without FPU or or multicore support on the Spike simulation platform. There is *no verification* for this platform.
## Upgrade Notes ---
# Full changelog Refer to the git log in https://github.com/seL4/seL4 using `git log 9.0.0..9.0.1`
# More details See the [9.0.1 manual](http://sel4.systems/Info/Docs/seL4-manual-9.0.1.pdf) included in the release or ask on the mailing list!# CAmkES Version camkes-3.3.0 Release
----
# CAmkES Version camkes-3.4.0 Release
Announcing the release of `` with the following changes:
camkes-3.4.0 2018-04-18
Using seL4 version 9.0.1
## Changes
## Upgrade Notes ---
# Full changelog Use `git log camkes-3.3.0..camkes-3.4.0` in https://github.com/seL4/camkes-tool
# More details See the
[documentation](https://github.com/seL4/camkes-tool/blob/camkes-3.4.0/docs/index.md) or ask on the mailing list! _______________________________________________ Devel mailing list Devel@sel4.systems https://sel4.systems/lists/listinfo/devel
_______________________________________________ Devel mailing list Devel@sel4.systems https://sel4.systems/lists/listinfo/devel
-- Hesham