Re: [seL4] Porting sel4 on RISCV architecture

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"Sathya" == Sathya Narayanan N writes:

Sathya> Query - I simulated sel4test on spike and then I am trying to Sathya> port it on FPGA. We have UART to be mapped to 0x11400 address Sathya> location. I set scan-> reg to this value. The Spike platform has only a UART and a timer, both of which are stolen by the proxy-tk kernel. seL4 calls into the proxy kernel, which runs in machine mode, to use them. Sathya> I understood, incase of simulation, the DTB argument passed to Sathya> init_first_hart function comes from spike simulator (file - Sathya> sim.cc). Now, for FPGA I want to pass the DTB value to the Sathya> init_first_hart() function. I am planning to write a DTS file Sathya> and somehow read the ​data from ​ DTS file here. ​ I am trying Sathya> to know, what is the right method to do for SEL4 ?​ seL4 doesn't use the DTB at all. And so far we haven't ported seL4 to a RSIC-V platform with any real devices. -- Dr Peter Chubb Tel: +61 2 9490 5852 http://ts.data61.csiro.au/ Trustworthy Systems Group Data61, CSIRO (formerly NICTA)