On Mon, Jul 16, 2018 at 10:54 AM, <Peter.Chubb(a)data61.csiro.au> wrote:
>>>> "Sathya" == Sathya Narayanan N <sathya281(a)gmail.com>
Sathya> Hi Peter,
Sathya> Thanks. I am trying to port it to a RISCV running FPGA and
Sathya> show the output through UART ? Is it possible with just the
Sathya> upstreamed code or something I need to do ?
If there is a proxy-kernel that handles the UART on your FPGA then I'd
expect the upstream code to work. But as I said, we haven't tried
Adding to Peter's reply, the current implementation of seL4 relies on
riscv-pk for outputing characters. The current behaviour of the proxy
kernel is that it uses the UART device if found, otherwise it uses
HTIF. seL4 isn't affected by any of this.
So assuming that you have a proper UART device that riscv-pk can
inspect (from DTB), riscv-pk will use it whenever seL4 wants to output
I've tried this on QEMU -freedomu and -virt platforms that use SiFive
UART and UART16550 respectively, and on VC707 FPGA with SiFive's UART.
Dr Peter Chubb Tel: +61 2 9490 5852 http://ts.data61.csiro.au/
Trustworthy Systems Group Data61, CSIRO (formerly NICTA)
Devel mailing list