I pushed my local seL4/RISC-V work to GitHub which contains the
following new features:
* A new option to run seL4 in machine mode.
* A port of seL4 to QEMU's SiFiveU and virt platforms.
* DTB parsing in seL4 to read and use UARTs when available.
* Ported seL4 to run on VC707 FPGA Freedom Unleashed platform.
* Initial Benchmarking support in seL4.
* Initial sel4bench port that can measure IPC and trap timing.
Link for more details: