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Hi Gernot,
thanks for sharing your thoughts. I am entering the thread here as I my thoughts go into a similar direction. We last year mentored Hesham's GSoC project of porting seL4 to the RISC-V architecture and think in the direction of TEEs for a GSoC this year. In my job I have worked a lot with GP-compliant TEEs the last year and it would be great if you could share your opinions on my thought process.
First of all, RISC-V has four execution levels that are more or less similar to ARM's EL0 to EL3. My starting point for a GP-compliant TEE would naturally be OP-TEE, and of course seL4.
These are the options and my thought process:
* Porting OP-TEE plainly to RISC-V: Would be a nice project, but I would prefer a portable solution. When porting directly, either OP-TEE can serve as SM or more preferably there should be a RISC-V equivalent of ARM-TF.
* Porting OP-TEE on top of seL4: That would be para-virtualizing OP-TEE os. The communication between secure world and non-secure world is mapped to seL4 communication.
* Porting OP-TEE functions as seL4 services: This is maybe actually the best way to handle it. All threading and separation is handled by seL4, Trusted Applications run as seL4 containers with the GP-API, and the services (encrypted storage, crypto functions etc.) are running as seL4 services, too.
* For the latter two, one thing that remains is similar to the original thread question: The non-secure operating systems need to be para-virtualized ideally, right? Or can seL4 currently work as a hypervisor? The question remains is then how the communication between non-secure and secure world is dispatched, or is there something like a lowest exception level secure monitor needed. Sorry, if I overlooked this part until now.
Thanks a lot for your input.
Best, Stefan
- -- Stefan Wallentowitz Staff Engineer
Simless GmbH, Zweigstelle/Branch München Adresse/Address: Freibadstr. 30, 81543 München, Germany Email: stefan@simless.com Web: www.simless.com
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