I am trying to bring up sel4 on tegra Tx2 platform using tegra Tx1 as
I tweaked the important changes of UART,Timer configuration and IRQ number
and also GIC controller, GIC distributor configuration w.r.t Tx2
after loading and booting the Tx2 board sel4 enter into init kernel to
initialize the kerenl memory map for GIC and UART devices then control
transfer to user space. I underdtand from ref manual both Tx1 and Tx2 using
the same clock and baud rate for UART configuration.
## Starting application at 0x82000000 ...
ELF-loader started on CPU: ARM Ltd. Cortex-A57 r1p3
load_elf : image_size 0x230000
ELF-loading image 'kernel'
load_elf : image_size 0x5e9000
ELF-loading image 'sel4test-driver'
Enabling MMU and paging
Jumping to kernel-image entry point...
Also try to add debug print in the init kernel thread to understand the
virtual memory set-up but its crashed with synchronous exception.
It indicates that the UART driver till not available to log the messages
this was seen in Tx1 and Tx2. Not able to check/debug further on this issue.
Also experimented with various arbitrary address for UARTA_PPTR and
GIC_PPTR because Tx1 UARTA has 64byte size in case of Tx2 its 1MB.but still
nothing has improved the state remain same.
I completely walk through the sel4 boot and arm MMU code.I do not see any
board specific changes in this code apart from UART,GIC configuration and
IRQ number. The assembly code of MMU mainly setting up TCR ,TTBR , TLB
invalidation and pagetable setup for arma-57.
Please let me know your thought on this issue and how do debug this kind of