Hi seL4 Dev team,
Can someone explain the reason (share the reference) to invalidate the
local TLB during kernel vspace activation as part CPU initialisation.
The Tx2 board stuck while performing this operation. As per my
understanding both Tx1 and Tx2 are using same A57 core. so the TLB
initialisation and invalidation remain same for Tx2 and should not stuck
during invalidation.Please correct me if anything wrong here.
I understand from that instruction (tlbi vmalle1) which is invalidating
stage 1 entries associated to the current VMID. Also from arm mmu code the
seL4 setting up (TCR_EL1) TCR register addressing space as 48bit, ASID as
16bit and page table setup 4k granular size.
I am using MRS macro to dump the spsr_el1 and dspsr_el0 register to see the
state of processor but its throwing synchronous exception. Do we have any
other option to dump all the register content to see the state of processor
like we have one in 'sel4debug_dump_registers' which is used in sel4test
code.
Regards,
Muneeswaran R
