Hello,
I'm trying to understand the current situation of the MCS branch.
Our setup:
- Microchip Polarfire SoC (1xE51 RV64IMAC + 4xU54 RV64IMAFD)
We are starting to "play" with threads but when coming to the scheduling of them, I'm a bit lost.
If I understand correctly, the latest version of seL4 (12.1.0) if compatible with RV64IMAFD, so floating point operations included.
The latest MCS version (10.1.1-mcs) on the contrary is only RV64IMAC so no FPU support.
I haven't seen any MR nor discussion about including that FPU support when using RISCV processors... Am I correct in here? or I am missing something?
(It's not really clear to me when I read the docs to be honest)
Thanks for your support.
-
David.