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Caught cap fault in send phase at address 0x0
by Andrew Shruhan 22 Sep '15

22 Sep '15

Hello, I am attempting to create a simple program opening up a serial port on the Sabrelight. Attached is the source code and below is the console output. On other sel4 blogs with this problem uboot may have been the issue. I have used the u-boot as discribed on the supported hardware->sabrelight page with the same outcome. Any help would be appreciated. Thanks, U-Boot 2009.08-dirty (Sep 17 2015 - 14:58:04) CPU: Freescale i.MX6 family TO1.2 at 792 MHz Temperature: 36 C, calibration data 0x56a4bc7d mx6q pll1: 792MHz mx6q pll2: 528MHz mx6q pll3: 480MHz mx6q pll8: 50MHz ipg clock : 66000000Hz ipg per clock : 66000000Hz uart clock : 80000000Hz cspi clock : 60000000Hz ahb clock : 132000000Hz axi clock : 264000000Hz emi_slow clock: 132000000Hz ddr clock : 528000000Hz usdhc1 clock : 198000000Hz usdhc2 clock : 198000000Hz usdhc3 clock : 198000000Hz usdhc4 clock : 198000000Hz nfc clock : 24000000Hz Board: MX6Q-SABRELITE:[ POR] Boot Device: I2C I2C: ready DRAM: 1 GB MMC: FSL_USDHC: 0,FSL_USDHC: 1 JEDEC ID: 0xbf:0x25:0x41 Reading SPI NOR flash 0xc0000 [0x2000 bytes] -> ram 0x276009b8 SUCCESS *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Net: got MAC address from IIM: 00:19:b8:01:fd:6d FEC0 [PRIME] Hit any key to stop autoboot: 0 mmc1 is current device -- Trying fat on SD 1, partition 1 reading sel4-image 344564 bytes read ## Starting application at 0x20000000 ... ELF-loader started on CPU: ARM Ltd. Cortex-A9 r2p10 paddr=[20000000..2004c01f] ELF-loading image 'kernel' paddr=[10000000..10031fff] vaddr=[e0000000..e0031fff] virt_entry=e0000000 ELF-loading image 'hello-1' paddr=[10032000..1003ffff] vaddr=[8000..15fff] virt_entry=803c Enabling MMU and paging Jumping to kernel-image entry point... Bootstrapping kernel Caught cap fault in send phase at address 0x0 while trying to handle: vm fault on data at address 0x0 with status 0x7 in thread 0xffdfd900 "rootserver" at address 0x804 -- -Andrew Andrew P. Shruhan Research and Development Engineer III DocBox, Inc. 320 Nevada St Newton MA, 02460 Work: 857-598-2819 ext. 117 www.docboxmed.com <http://www.docboxinc.com/>

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Question about upstream
by Harish Pillay 9v1hp 20 Sep '15

20 Sep '15

Hi. I came across seL4 yesterday and have not spent too much time on it. I have not found anything specific to my question in the FAQ yet, so I am posing it here: has the work done by seL4 been accepted upstream? If not, any reason why it has not been accepted yet? Thanks. Harish

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Roadmap and Developers Day announcements
by Gernot Heiser 16 Sep '15

16 Sep '15

Dear developers, Those of you who aren’t (yet) subscribed to announce(a)sel4.systems might have missed this: we announced - the seL4 roadmap: https://sel4.systems/pipermail/announce/2015/000007.html - the second Developers Day: https://sel4.systems/pipermail/announce/2015/000008.html Gernot ________________________________ The information in this e-mail may be confidential and subject to legal professional privilege and/or copyright. National ICT Australia Limited accepts no liability for any damage caused by this email or its attachments.

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Mysterious Label Before sysenter
by Corey Richardson 16 Sep '15

16 Sep '15

For example, here: https://github.com/seL4/seL4/blob/master/libsel4/arch_include/x86/sel4/arch… What use is the label? Does it align the instruction or do other ABI-important things? -- /cmr

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x86-64
by Raymond Jennings 13 Sep '15

13 Sep '15

Does seL4 support x86-64 with 64-bit virtual address spaces?

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Adding a Rust kernel interface generator
by Corey Richardson 11 Sep '15

11 Sep '15

Hello, As part of the robigalia [0] project I must create a Rust interface to the kernel. I'm using the XML from kernel/libsel4 and have been creating a "new" generator by copying the existing Python scripts. Should I send a patch upstream once this is suitably complete, or should I maintain this completely externally? [0] - https://github.com/robigalia -- /cmr

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how to detect the number of CPUs in the system
by 杰尔米 01 Sep '15

01 Sep '15

Hi all, i want to get the number of CPUs in the system and how many cores in one CPU. how to do that? Thanks! Jeremy Li

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The pt/pd/as abstraction vs software TLBs
by Raymond Jennings 01 Sep '15

01 Sep '15

Hey, quick question. This is just hypothetical, but would making management of pagetables/pagedirectories a low level literal operation hurt seL4's portability to other architectures that might not even use page tables? I could be mistaken but I think there's some archs out there that only have software TLBs (openrisc IIRC among them) Please forgive me if I'm mistaken but my recent question about memory abstraction reminded me about this.

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sharing memory between processes
by Raymond Jennings 01 Sep '15

01 Sep '15

Is there an easy way for one task to share address space with another task directly or does it have to go through the kernel/os and be emulated? I noticed that support for mapping memory is mostly low level assignment of physical frames to virtual frames via page tables, unlike Mach which uses memory objects.

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virtual memory abstraction
by Raymond Jennings 31 Aug '15

31 Aug '15

I noticed that unlike mach, L4 does not directly manage virtual memory, but instead farms out address space, page directory, and page table capabilities to userspace and lets userspace decide what pages to map and where. Does this imply that virtual memory abstraction is userspace responsibility?

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