May 2022 - Devel - lists.sel4.systems

seL4 test on x86
by Yevgeny Lavrov 30 Jan '25

30 Jan '25

Hello, I'm new to seL4 and I'm just doing it for learning purpose. I'm trying to run seL4 test suite or simple hello world task from seL4 tutorials on the real hardware. So far I had no problems compiling seL4 test suite and running via QEMU for both x32 and x64 platforms. However, when I try to run it on the actual hardware following Running on real hardware tutorial for x86 I end up with no output at all and no error msgs that can give me a clue on where something went wrong. After compiling seL4test for x86, I ended up with two images in sel4_dir/images/ folder. Copied them over to /boot/sel4/ folder and created a new GRUB2 entry that looks like this menuentry “seL4 test suite” --class os { load video insmod gzio insmod part_msdos insmod ext2 set root=’(hd0,msdos5)’ multiboot /boot/sel4/kernel-ia32-pc99 module /boot/sel4/sel4test-driver-image-ia32-pc99 } update grub, restart and select the new entry from GRUB menu. I end up with blinking cursor on the top-left side of the screen. Please advise.

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Stuck during invalidate local TLB in Tx2
by Muneeswaran Rajendran 16 Oct '24

16 Oct '24

Hi seL4 Dev team, Can someone explain the reason (share the reference) to invalidate the local TLB during kernel vspace activation as part CPU initialisation. The Tx2 board stuck while performing this operation. As per my understanding both Tx1 and Tx2 are using same A57 core. so the TLB initialisation and invalidation remain same for Tx2 and should not stuck during invalidation.Please correct me if anything wrong here. I understand from that instruction (tlbi vmalle1) which is invalidating stage 1 entries associated to the current VMID. Also from arm mmu code the seL4 setting up (TCR_EL1) TCR register addressing space as 48bit, ASID as 16bit and page table setup 4k granular size. I am using MRS macro to dump the spsr_el1 and dspsr_el0 register to see the state of processor but its throwing synchronous exception. Do we have any other option to dump all the register content to see the state of processor like we have one in 'sel4debug_dump_registers' which is used in sel4test code. Regards, Muneeswaran R

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Questions about Memory Management in seL4
by Daniel Wang 19 May '23

19 May '23

Hi all, Sorry to bother, I have some basic questions about seL4 memory management. Can someone help me? 1. where is the kernel’s address space? I know there are basically three methods: a) separate virtual address space, e.g. through changing page tables on entry into privileged mode to access b) physical space, e.g. through disable automatic hardware translation of virtual addresses on entry into privilege mode c) privilege region in each process’s virtual address space, e.g. through page table to map kernel address into use-mode process. My question is which of this is being used by seL4 microkernel? 2. Objects like CSpace, VSpace, CNode, TCB, Endpoint, etc. are called kernel objects, but it seems all dynamically allocated in thread running/creating time. Are those objects (e.g. Figure 3.3 in seL4 manual) in kernel space or in user space? 3. I read that after the kernel boot up, it passes all resources, untyped memory to the first thread. Are those untyped memory physical memory or virtual memory in a single page? The reason I ask is I’m learning the code of the UNSW AOS project (two of the assignment projects are implementing frame and papers). I’m confused that before the implementation of frames and pages what kind of memory is passed to the the first thread? I saw int AOS project, it uses ut_table_init(), ut_steal_mem(), I wonder what kind of memory it operates on? Thanks -Dan

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Anyone using capability transfer in an seL4 project? Looking for examples for research
by sjwebb＠student.unimelb.edu.au 12 Jul '22

12 Jul '22

Hi all, I'm working on a Masters research project looking into mapping an object-capability programming language onto seL4, in a way that includes some kind of mapping from the language object capabilities onto seL4's capabilities (or vice versa). I'm at a stage of the project now where it would be really helpful to have some 'motivating examples' for transferring caps between threads/CSpaces. So I was hoping I could reach out to other seL4 developers to see if they had built any systems that made extensive use of moving capabilities around. Ideally, in an ocap language, these examples would be much easier to program than they currently would be in C... The simplest example I can think of is a memory allocation server, but that wouldn't necessarily involve handing caps on beyond the one (requesting) process, which is the kind of thing I think more interesting examples would comprise of. Cheers, Stewart Webb [Masters Research student at University of Melbourne]

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sel4 on bare-metal | Questions and comments
by Sid Agrawal 10 Jun '22

10 Jun '22

Hi, As per instructions from here[1, 2], I tried booting seL4 on an x86_64-desktop, x86_64-server as RPi4. I was able to get it to work on RPi4 with one minor change to the instructions, but I could not boot it on the x86_64-desktop or the x86_64-server. Below is my experience and the issues I faced. RPi4 ------ Spec: 8GB standard Rpi4 The final command "fatload mmc 0 0x10000000 sel4test-driver-image-arm-bcm2711" gave the following error: ** Reading file would overwrite reserved memory ** Failed to load 'sel4test-driver-image-arm-bcm2711 I could get around it by using a load address that was smaller by a factor of 0x10.( 0x1000000 instead of 0x10000000 i.e. one less zero). I cannot claim I understand why the first address failed and the second worked. Any pointers on that would help. After the change in the address, I saw the sel4 tests run as expected. x86_64 server ------------------ Spec: Dell R520, two quad-core Xeons (E5-2407 v2 @ 2.40GHz), 32GB of memory. The server's serial is redirected to the IPMI console. On the IPMI console, I see many messages related to the bios, etc. And finally, I see this: MBR SYSLINUX 6.04 EDD [...] Loading sel4kernel... ok Loading rootserver... ok But nothing after this. Any thoughts of what could be going wrong here? I did not see any sel4 prints. x86_64 Desktop ---------------------- Spec: Core 2 Quad, 4 GB ram It was able to find the pinout for the serial port on the motherboard and connected to it(just like for RP). There was no output on the serial console. Even when bios-related messages were printed on the monitor, there was no output on the serial pins. I might need to enable the serial output on those pins in the bios or something similar. Fortunately, even though the serial pins did not have any output, the monitor output was the same as for the server. Unfortunately, it did not get any farther along than the server. MBR SYSLINUX 6.04 EDD [...] Loading sel4kernel... ok Loading rootserver... ok Any pointers here would be helpful. Thanks, Sid UBC Graduate Student ARM Research Intern [1] https://docs.sel4.systems/Hardware/IA32 [2] https://docs.sel4.systems/Hardware/Rpi4.html

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Running RISC-V seL4 in QEMU 7.0.50
by porter.188＠osu.edu 03 Jun '22

03 Jun '22

Hello, I'm trying to run sel4test in QEMU 7.0.50. I can compile successfully but sel4test hangs at "Jumping to kernel-image entry point...". Is there something different required now that sel4 is using OpenSBI? $ qemu-system-riscv64 -nographic -serial mon:stdio -m size=4095M -bios none -kernel images/sel4test-driver-image-riscv-spike OpenSBI v0.8 ____ _____ ____ _____ / __ \ / ____| _ \_ _| | | | |_ __ ___ _ __ | (___ | |_) || | | | | | '_ \ / _ \ '_ \ \___ \| _ < | | | |__| | |_) | __/ | | |____) | |_) || |_ \____/| .__/ \___|_| |_|_____/|____/_____| | | |_| Platform Name : ucbbar,spike-bare,qemu Platform Features : timer,mfdeleg Platform HART Count : 1 Boot HART ID : 0 Boot HART ISA : rv64imafdcsuh BOOT HART Features : pmp,scounteren,mcounteren BOOT HART PMP Count : 16 Firmware Base : 0x80000000 Firmware Size : 96 KB Runtime SBI Version : 0.2 MIDELEG : 0x0000000000001666 MEDELEG : 0x0000000000f0b509 PMP0 : 0x0000000080000000-0x000000008001ffff (A) PMP1 : 0x0000000000000000-0xffffffffffffffff (A,R,W,X) ELF-loader started on (HART 0) (NODES 1) paddr=[80200000..8066a037] Looking for DTB in CPIO archive...found at 802d2128. Loaded DTB from 802d2128. paddr=[84020000..84020fff] ELF-loading image 'kernel' to 84000000 paddr=[84000000..8401ffff] vaddr=[ffffffff84000000..ffffffff8401ffff] virt_entry=ffffffff84000000 ELF-loading image 'sel4test-driver' to 84021000 paddr=[84021000..843f6fff] vaddr=[10000..3e5fff] virt_entry=1b982 Enabling MMU and paging Jumping to kernel-image entry point...

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Re: Reminder seL4 developer hangout
by Isaac Beckett 31 May '22

31 May '22

Oh boy, 3AM! I hope to make it, but if I sound tired, that’s why. > Date: Mon, 30 May 2022 00:08:16 +0000 > From: Birgit Brecknell <birgit.brecknell(a)unsw.edu.au> > Subject: [seL4] Reminder seL4 developer hangout > To: "devel(a)sel4.systems" <devel(a)sel4.systems> > Message-ID: <MEAPR01MB44693624005ED9CB8CFDD3A7DEDD9(a)MEAPR01MB4469.aus > prd01.prod.outlook.com> > Content-Type: text/plain; charset="iso-8859-1" > > Hi all > > A friendly reminder that the seL4 developer hangout is on again this week: > > Wed, Jun 1, 7am (UTC), Topics: (open) > > * Sydney: Wed, Jun 1, 5pm > * Central Europe: Wed, Jun 1, 9am > * US Pacific Time: Wed, Jun 1, 12 midnight > > Zoom link: https://unsw.zoom.us/j/82640784431 > > cheers > Birg > > > > --- > > Dr. Birgit Brecknell > > Project Officer > > Trustworthy Systems, UNSW, birgit.brecknell(a)unsw.edu.au<mailto:birgit.brecknell@unsw.edu.au> > > seL4 Foundation, birgit(a)sel4.systems<mailto:birgit@sel4.systems> > > 0433 880 571 > > > > Mon 9am-5pm > > Wed 9am-12pm > > Fri 9am-5pm

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Reminder seL4 developer hangout
by Birgit Brecknell 30 May '22

30 May '22

Hi all A friendly reminder that the seL4 developer hangout is on again this week: Wed, Jun 1, 7am (UTC), Topics: (open) * Sydney: Wed, Jun 1, 5pm * Central Europe: Wed, Jun 1, 9am * US Pacific Time: Wed, Jun 1, 12 midnight Zoom link: https://unsw.zoom.us/j/82640784431 cheers Birg --- Dr. Birgit Brecknell Project Officer Trustworthy Systems, UNSW, birgit.brecknell(a)unsw.edu.au<mailto:birgit.brecknell@unsw.edu.au> seL4 Foundation, birgit(a)sel4.systems<mailto:birgit@sel4.systems> 0433 880 571 Mon 9am-5pm Wed 9am-12pm Fri 9am-5pm

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Running RISC-V seL4 in QEMU 7.0.50
by porter.188＠osu.edu 28 May '22

28 May '22

Hello, I am trying to run a simple hello world project in seL4 RISC-V in QEMU. It seems to hang at "Jumping to kernel-image entry point..." This same behavior happens on sel4test as well. In the past this was due to a bios option in QEMU changing. Is there something else going on here? I know seL4 uses OpenSBI instead of BBL for RISC-V but is there something else in QEMU or some other switch we need to add? The commands I run are: $ qemu-system-riscv64 -machine spike -cpu rv64 -nographic -serial mon:stdio -m size=4095M -bios none -kernel images/sel4test-driver-image-riscv-spike OpenSBI v0.8 ____ _____ ____ _____ / __ \ / ____| _ \_ _| | | | |_ __ ___ _ __ | (___ | |_) || | | | | | '_ \ / _ \ '_ \ \___ \| _ < | | | |__| | |_) | __/ | | |____) | |_) || |_ \____/| .__/ \___|_| |_|_____/|____/_____| | | |_| Platform Name : ucbbar,spike-bare,qemu Platform Features : timer,mfdeleg Platform HART Count : 1 Boot HART ID : 0 Boot HART ISA : rv64imafdcsuh BOOT HART Features : pmp,scounteren,mcounteren BOOT HART PMP Count : 16 Firmware Base : 0x80000000 Firmware Size : 96 KB Runtime SBI Version : 0.2 MIDELEG : 0x0000000000001666 MEDELEG : 0x0000000000f0b509 PMP0 : 0x0000000080000000-0x000000008001ffff (A) PMP1 : 0x0000000000000000-0xffffffffffffffff (A,R,W,X) ELF-loader started on (HART 0) (NODES 1) paddr=[80200000..8066a037] Looking for DTB in CPIO archive...found at 802d2128. Loaded DTB from 802d2128. paddr=[84020000..84020fff] ELF-loading image 'kernel' to 84000000 paddr=[84000000..8401ffff] vaddr=[ffffffff84000000..ffffffff8401ffff] virt_entry=ffffffff84000000 ELF-loading image 'sel4test-driver' to 84021000 paddr=[84021000..843f6fff] vaddr=[10000..3e5fff] virt_entry=1b982 Enabling MMU and paging Jumping to kernel-image entry point...

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Getting Badge Value of a badged EP capability
by Sid Agrawal 22 May '22

22 May '22

Hi seL4-devs and users, I have a question about implementing server and client using badged endpoints. Below I have laid out the scenario, the issue, and some questions. *Scenario* I have a userspace server that implements the functionality for an object(say type obj_T1). The server hands out badged-endpoints to clients to interact with this object. The badge is the virtual address of the object's struct in the server’s virtual address space. A client can interact with the object by sending messages on this badged endpoint. The client never learns the badge value. The kernel extracts the badged value when the server receives a message on this endpoint. By using the badge value, the server knows which object the client is trying to manipulate. The same PD, which implements the 1st server, also implements another server(in a separate thread, but same address space) for another object type (say type obj_T2). The server follows the same paradigm of handing out badged endpoints and using the badges values to keep track of the object. *Issue* I have a scenario where the client wants to invoke the functionality of obj_T1. This functionality needs access to obj_T2 as well. The client has badged EP caps to both objects. The client can invoke the badged EP handed out by server-1 for obj_T1 and give the badged EP of obj_T2 as an extraCap in the IPC message(or vice versa). Since the server has no way to look up the badge of the second cap, it cannot look up the underlying object for obj_T2. So my questions are: 1. Is there a way for a PD to look up the badge value of badged EP? I think the answer is no, but I thought I would still ask. 2. Is my idea of using the badge to keep track of the underlying object on the right track? Is there a better way of going about doing it? 3. As a potential solution, I can extend my server to add a new function, say GETID, which returns the badge value of a given object(i.e., EP). Since I know that the server always badges the EP with the virtual address of the struct, it is a trivial call to implement. But I somehow feel like this is not a neat idea, not quite sure why. Thanks for the help, everyone! Sid CS Graduate Student @ UBC sid-agrawal.ca

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