- Devel - lists.sel4.systems

libsel4cspace and IPC
by Will Korteland 27 Sep '15

27 Sep '15

Hi, I'm trying to implement a "create endpoint" syscall as a continuation of my AOS project last year. I'm using the following code to create and endpoint in the current threads's cspace (using libsel4cspace): https://gist.github.com/anonymous/8294aa47ad351e4d4066 When this code runs, seL4 prints the following during the cspace_ut_retype_addr call: <<seL4 [decodeUntypedInvocation/128 Tffeead00 @b330]: Untyped Retype: Invalid destination address.>> This error comes from inside libsel4cspace, specifically where it calls seL4_Untyped_RetypeAtOffset(). I've read the libsel4cspace documentation and enabled CSPACE_DEBUG, but nothing from the output looks amiss (I'm not an expert though, and I can post the relevant debug output). Have I done anything wrong in the code above? Thanks, - Will

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How to modify timer server in refos
by ぷ风过无痕?? 27 Sep '15

27 Sep '15

I want to transplant the Refos into the ZYNQ board,Now everything is ok,except the timer server. Could you give me some advices about how to modify timer server's file device_timer.c . ------------------ Original ------------------ From: "devel-request";<devel-request(a)sel4.systems>; Date: Thu, Sep 24, 2015 10:00 AM To: "devel"<devel(a)sel4.systems>; Subject: Devel Digest, Vol 16, Issue 12 Send Devel mailing list submissions to devel(a)sel4.systems To subscribe or unsubscribe via the World Wide Web, visit https://sel4.systems/lists/listinfo/devel or, via email, send a message with subject or body 'help' to devel-request(a)sel4.systems You can reach the person managing the list at devel-owner(a)sel4.systems When replying, please edit your Subject line so it is more specific than "Re: Contents of Devel digest..." Today's Topics: 1. Reminder: Developers Day registration closes Monday (Gernot Heiser) ---------------------------------------------------------------------- Message: 1 Date: Wed, 23 Sep 2015 05:58:01 +0000 From: Gernot Heiser <gernot(a)nicta.com.au> To: seL4 <devel(a)sel4.systems> Subject: [seL4] Reminder: Developers Day registration closes Monday Message-ID: <FD16E4F0-FD7A-494C-9432-AF1C4903E750(a)nicta.com.au> Content-Type: text/plain; charset="us-ascii" Details at https://sel4.systems/Community/Devdays/ Gernot ________________________________ The information in this e-mail may be confidential and subject to legal professional privilege and/or copyright. National ICT Australia Limited accepts no liability for any damage caused by this email or its attachments. ------------------------------ Subject: Digest Footer _______________________________________________ Devel mailing list Devel(a)sel4.systems https://sel4.systems/lists/listinfo/devel ------------------------------ End of Devel Digest, Vol 16, Issue 12 *************************************

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Reminder: Developers Day registration closes Monday
by Gernot Heiser 23 Sep '15

23 Sep '15

Details at https://sel4.systems/Community/Devdays/ Gernot ________________________________ The information in this e-mail may be confidential and subject to legal professional privilege and/or copyright. National ICT Australia Limited accepts no liability for any damage caused by this email or its attachments.

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Caught cap fault in send phase at address 0x0
by Andrew Shruhan 22 Sep '15

22 Sep '15

Hello, I am attempting to create a simple program opening up a serial port on the Sabrelight. Attached is the source code and below is the console output. On other sel4 blogs with this problem uboot may have been the issue. I have used the u-boot as discribed on the supported hardware->sabrelight page with the same outcome. Any help would be appreciated. Thanks, U-Boot 2009.08-dirty (Sep 17 2015 - 14:58:04) CPU: Freescale i.MX6 family TO1.2 at 792 MHz Temperature: 36 C, calibration data 0x56a4bc7d mx6q pll1: 792MHz mx6q pll2: 528MHz mx6q pll3: 480MHz mx6q pll8: 50MHz ipg clock : 66000000Hz ipg per clock : 66000000Hz uart clock : 80000000Hz cspi clock : 60000000Hz ahb clock : 132000000Hz axi clock : 264000000Hz emi_slow clock: 132000000Hz ddr clock : 528000000Hz usdhc1 clock : 198000000Hz usdhc2 clock : 198000000Hz usdhc3 clock : 198000000Hz usdhc4 clock : 198000000Hz nfc clock : 24000000Hz Board: MX6Q-SABRELITE:[ POR] Boot Device: I2C I2C: ready DRAM: 1 GB MMC: FSL_USDHC: 0,FSL_USDHC: 1 JEDEC ID: 0xbf:0x25:0x41 Reading SPI NOR flash 0xc0000 [0x2000 bytes] -> ram 0x276009b8 SUCCESS *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Net: got MAC address from IIM: 00:19:b8:01:fd:6d FEC0 [PRIME] Hit any key to stop autoboot: 0 mmc1 is current device -- Trying fat on SD 1, partition 1 reading sel4-image 344564 bytes read ## Starting application at 0x20000000 ... ELF-loader started on CPU: ARM Ltd. Cortex-A9 r2p10 paddr=[20000000..2004c01f] ELF-loading image 'kernel' paddr=[10000000..10031fff] vaddr=[e0000000..e0031fff] virt_entry=e0000000 ELF-loading image 'hello-1' paddr=[10032000..1003ffff] vaddr=[8000..15fff] virt_entry=803c Enabling MMU and paging Jumping to kernel-image entry point... Bootstrapping kernel Caught cap fault in send phase at address 0x0 while trying to handle: vm fault on data at address 0x0 with status 0x7 in thread 0xffdfd900 "rootserver" at address 0x804 -- -Andrew Andrew P. Shruhan Research and Development Engineer III DocBox, Inc. 320 Nevada St Newton MA, 02460 Work: 857-598-2819 ext. 117 www.docboxmed.com <http://www.docboxinc.com/>

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Question about upstream
by Harish Pillay 9v1hp 20 Sep '15

20 Sep '15

Hi. I came across seL4 yesterday and have not spent too much time on it. I have not found anything specific to my question in the FAQ yet, so I am posing it here: has the work done by seL4 been accepted upstream? If not, any reason why it has not been accepted yet? Thanks. Harish

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Roadmap and Developers Day announcements
by Gernot Heiser 16 Sep '15

16 Sep '15

Dear developers, Those of you who aren’t (yet) subscribed to announce(a)sel4.systems might have missed this: we announced - the seL4 roadmap: https://sel4.systems/pipermail/announce/2015/000007.html - the second Developers Day: https://sel4.systems/pipermail/announce/2015/000008.html Gernot ________________________________ The information in this e-mail may be confidential and subject to legal professional privilege and/or copyright. National ICT Australia Limited accepts no liability for any damage caused by this email or its attachments.

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Mysterious Label Before sysenter
by Corey Richardson 16 Sep '15

16 Sep '15

For example, here: https://github.com/seL4/seL4/blob/master/libsel4/arch_include/x86/sel4/arch… What use is the label? Does it align the instruction or do other ABI-important things? -- /cmr

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x86-64
by Raymond Jennings 13 Sep '15

13 Sep '15

Does seL4 support x86-64 with 64-bit virtual address spaces?

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Adding a Rust kernel interface generator
by Corey Richardson 11 Sep '15

11 Sep '15

Hello, As part of the robigalia [0] project I must create a Rust interface to the kernel. I'm using the XML from kernel/libsel4 and have been creating a "new" generator by copying the existing Python scripts. Should I send a patch upstream once this is suitably complete, or should I maintain this completely externally? [0] - https://github.com/robigalia -- /cmr

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how to detect the number of CPUs in the system
by 杰尔米 01 Sep '15

01 Sep '15

Hi all, i want to get the number of CPUs in the system and how many cores in one CPU. how to do that? Thanks! Jeremy Li

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